1. Field of the Invention
This invention relates to semiconductor devices and in particular to integrated circuits of smaller size, higher speed and higher packing density than heretofore obtained, and to the process of making them.
2. Prior Art
Various ways have been proposed to isolate electrically a plurality of pockets of semiconductor material in each of which one or more circuit elements can be formed. Among the ways proposed have been appropriately biased PN junctions (Noyce U.S. Pat. No. 3,117,260 issued Jan. 7, 1964), combinations of PN junctions and zones of intrinsic and extrinsic semiconducting materials (Noyce U.S. Pat. No. 3,150,299 issued Sep. 22, 1964), dielectric isolation (Frescura U.S. Pat. No. 3,391,023 issued Jul. 2, 1968) and mesa etching (Frescura et al U.S. Pat. No. 3,489,961 issued Jan. 13, 1970). Tucker and Barry, in patent application Ser. No. 845,822 filed Jul. 29, 1969, disclose the use of selectively-doped polycrystalline silicon to help isolate islands of single crystal silicon in which circuit elements can be formed.
After electrically-isolated pockets of semiconductor material are prepared, active and passive circuit elements are formed within or on the pockets. Many of these circuit elements are typically formed using the planar diffusion techniques disclosed by Hoerni in U.S. Pat. Nos. 3,025,589 and 3,064,167. In the planar process, the regions of each semiconductor pocket into which circuit elements are diffused are controlled by forming a diffusion mask from an insulation layer formed on the surface of the semiconductor material. After the desired elements have been formed in the semiconductor material, a conductive lead pattern is formed on the insulation and used to interconnect selected active and passive circuit elements into the desired circuit. Additional passive circuit elements can also be formed on the insulation and interconnected into the circuit. Such a structure is disclosed in Noyce U.S. Pat. No. 2,981,877 issued Apr. 25, 1961.
In the manufacture of integrated circuits, several problems arise. First, the area of the wafer required for the placement of the isolation regions between adjacent pockets of semiconductor material is a significant portion of the total wafer area. A large isolation area reduces the number of devices which can be placed in a wafer and thus lowers the "packing density" of the circuit elements formed in the wafer. Second, the leads formed on, and adherent to, the insulation on the wafer surface sometimes crack at steps in the insulation on the wafer surface. These steps are often quite steep. Third, several of the isolation techniques result in significant capacitances being introduced into the integrated circuit. While at low frequencies these capacitances do not affect the operation of the circuit, at high frequencies these capacitances can have a significant effect on circuit performance. Fourth, the prior art integrated circuits are usually formed in relatively thick (greater than 5 microns) epitaxial layers formed on support substrates. As a result, the operating speeds of the resulting devices are sometimes slower than desired. Fifth, the processes by which prior art integrated circuits are produced are relatively sensitive to defects in masks and to small errors in the sequential placement of masks on the device during the various process steps. Low defect masks, low defect masking procedures and proper alignment of the masks are important factors in obtaining good yields.
To eliminate cracks in the interconnect leads at steps in the insulation, J. S. So, in U.S. Pat. No. 3,404,451 issued Oct. 8, 1968 proposes to remove portions of this insulation from the wafer surface during processing. It has also been proposed to slope the edges of the insulation at the contact window. A different approach, disclosed by J. A. Appels, et al in an article entitled "Local Oxidation of Silicon and its Application in Semiconductor-Device Technology" Philips Research Reports 25, page 118 (1970), is to etch grooves into the semiconductor wafer adjacent those regions in which PN junctions are to be formed. The material exposed by the grooves is then thermally oxidized. If the process is properly controlled, the oxide surface and the surface of the semiconductor material approximately coplanar. An added advantage of this process, emphasized by Appels et al, is that the portion of the semiconductor wafer in which the impurity is diffused has a mesa-like shape. The resulting PN base-collector junction is substantially flat and has a higher breakdown voltage than does a dish-shaped PN junction but still contacts passivating oxide, as in the planar process.